Many portable products, such as cell phones, laptop computers, personal data assistants (PDAs) or the like, utilize a processor executing programs, such as, communication and multimedia programs. The processing system for such products includes a processor complex for processing instructions and data. The functional complexity of such portable products, other personal computers, and the like, requires high performance processors and memory. At the same time, portable products have limited energy sources in the form of batteries and provide high performance levels at reduced power levels to increase battery life. Many personal computers being developed today also are being designed to provide high performance at low power drain to reduce overall energy consumption.
Internal to the processor complex, memory elements, logic gates, and latches are used with increasing density as functionality, display density, storage density, and support for new communication and media compression standards grows. For example, many processors use long execution pipelines to achieve giga-hertz clock rates. Each stage in the execution pipeline requires a large plurality of latches as large data buses and instruction buses are latched at each pipeline stage.
Memory elements, such as register files, used in mobile devices require both high speed and low power consumption. For example, dynamic logic technology is used in register files for read access due to its speed advantage. Dynamic circuits use a precharge and a data evaluation phase to determine an output value. Due to the dynamic transitory nature of data read from dynamic logic elements, latches are used to hold the evaluated data values available on dynamic read bit lines. A hold latch, which favors catching logic zero values without using a clock signal, is generally termed a zero catcher. For example, a standard latch may use cross-coupled inverters to perform the following functions including to catch a logic level, to hold the logic level, and drive the logic level to succeeding logic stages. Such a standard latch may use excessive power when attempting to transition a held logic level to a different logic level. Since the output of the cross-coupled inverters may drive long wires or a plurality of loads, the transition power drain can be unacceptably large.